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| INTEGRATED CIRCUITS DATA SHEET TDA8376; TDA8376A I2C-bus controlled PAL/NTSC TV processors Objective specification File under Integrated Circuits, IC02 1996 Jan 26 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.2.1 8.2.2 9 10 11 11.1 12 13 13.1 13.2 14 15 15.1 15.2 15.2.1 15.2.2 15.3 15.3.1 15.3.2 15.3.3 16 17 18 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Video switches Integrated video filters, peaking and black stretcher Synchronization circuit Colour decoder RGB output circuit and black-current stabilization I2C-BUS SPECIFICATION Start-up procedure Inputs Input control bits Output control bits LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION Latch-up CHARACTERISTICS TEST AND APPLICATION INFORMATION East-West output stage Adjustment of geometry control parameters PACKAGE OUTLINES SOLDERING Introduction SDIP Soldering by dipping or by wave Repairing soldered joints QFP Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS TDA8376; TDA8376A 1996 Jan 26 2 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 1 FEATURES 2 TDA8376; TDA8376A GENERAL DESCRIPTION * Source selection with 2 CVBS inputs and a Y/C (or extra CVBS) input * Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor * Video identification circuit which is independent of the synchronization for stable On Screen Display (OSD) under `no-signal' conditions * Integrated chrominance trap with pre-shoot compensation and bandpass filters (automatically calibrated) * Integrated luminance delay line * Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function * Black stretcher circuit in the luminance channel * PAL/NTSC colour decoder with automatic search system * Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications * RGB control circuit with black-current stabilization and white point adjustment; to obtain a good grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment * Two linear RGB inputs and fast blanking * Horizontal synchronization with two control loops and alignment-free horizontal oscillator * Vertical count-down circuit * Geometry correction by modulation of the vertical and E-W drive * Vertical and horizontal zoom possibility for 16 : 9 applications (TDA8376A only) * I2C-bus control of various functions * Low dissipation (700 mW) * Small amount of peripheral components compared with competition ICs * Y, U and V inputs and outputs. The TDA8376 and TDA8376A are alignment-free I2C-bus controlled video processors which contain a PAL/NTSC colour decoder, luminance processor, sync processor, RGB-control and deflection processor. The circuits have been designed for use with the baseband chrominance delay line TDA4665 and for DC-coupled vertical and East-West (E-W) output stages. Both ICs are pin compatible. The TDA8376A has a flexible horizontal and vertical zoom possibility for 16 : 9 applications. The supply voltage for the ICs is 8 V. The ICs are available in an SDIP package with 52 pins and in a QFP package with 64 pins (see Chapter 4). The pin numbers indicated in this document are referenced to the SDIP52; SOT247-1 package; unless otherwise indicated. 1996 Jan 26 3 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 3 QUICK REFERENCE DATA SYMBOL Supply VP IP Input voltages V9,13(p-p) V27(p-p) V6(p-p) Vi(p-p) V38(p-p) V11(p-p) V30(p-p) V29(p-p) V19,20,21(p-p) I40 I47,48 I46 4 CVBS input voltage (peak-to-peak value) S-VHS luminance input voltage (peak-to-peak value) S-VHS chrominance input voltage (burst amplitude) (peak-to-peak value) RGB input voltage (peak-to-peak value) supply voltage supply current PARAMETER TDA8376; TDA8376A MIN. - - - - - - - - - - - TYP. MAX. - - - - - - - - - - - - - - UNIT 8.0 75 V mA 1.0 1.0 0.3 0.7 V V V V Output voltages TXT output voltage (peak-to-peak value) PIP output voltage (peak-to-peak value) -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) RGB output signal voltage amplitudes (peak-to-peak value) 1.0 1.0 525 675 2.0 - - - V V mV mV V Output currents horizontal output current vertical output current E-W drive output current ORDERING INFORMATION TYPE NUMBER TDA8376 TDA8376AH PACKAGE NAME SDIP52 QFP64 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT247-1 SOT319-2 10 1 0.5 mA mA mA 1996 Jan 26 4 dbook, full pagewidth 1996 Jan 26 8 5 Philips Semiconductors I2C-bus controlled PAL/NTSC TV processors BLOCK DIAGRAM FBI PH2LF SCO HOUT 43 41 39 40 EW GEOMETRY 46 49 VERTICAL GEOMETRY 47 48 50 51 2 EWD EHTO VDR(p) VDR(n) VSC Iref CBLK 18 BLKIN VP2 (+8 V) VP1 (+8 V) 37 SCL 3 I2C-BUS TRANSCEIVER SDA PH1LF 4 44 DECBG 5 VCO AND CONTROL ref 1 DECDIG 2nd LOOP AND HORIZONTAL OUTPUT CONTROL DACs 16 x 6 bits 2 x 4 bits SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER TDA8376(A) VIDEO IDENTIFICATION VERTICAL SYNC SEPARATOR ref FILTER TUNING BLACK STRETCHER WHITE POINT BLACK CURRENT STABILIZER BRI CONTR 22 21 20 19 BCLIN RO GO BO TRAP SW BAND PASS DELAY, PEAKING AND CORING SAT 5 SW HUE CVBS SWITCH 10 42 45 9 13 S-VHS SWITCH 6 7 11 38 DECFT 12 36 GND1 GND2 GND3 CVBSEXT CVBSINT CHROMA PIPO CVBS/TXT CVBS/Y SECref RGB MATRIX AND OUTPUT PAL/NTSC DECODER 35 DET 4.4 MHz 34 33 30 G-Y MATRIX AND SAT CONTROL 29 32 RYI 31 BYI LUMIN 28 27 RGB INPUT AND SWITCH 23 24 25 26 14 15 16 17 RGBIN2 RI2 GI2 BI2 RYO BYO 3.6 MHz TDA8376; TDA8376A RI1 GI1 BI1 RGBIN1 MGE078 TDA4665 XTAL2 XTAL1 LUMOUT Objective specification Fig.1 Block diagram (SDIP52; SOT247-1). Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 6 PINNING PIN SYMBOL SDIP52 DECDIG CBLK SCL SDA DECBG CHROMA CVBS/Y VP1 CVBSINT GND1 PIPO DECFT CVBSEXT RGBIN2 RI2 GI2 BI2 BLKIN BO GO RO BCLIN RI1 GI1 BI1 RGBIN1 LUMIN LUMOUT BYO RYO BYI RYI XTAL1 XTAL2 DET SECref VP2 CVBS/TXT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 QFP64 11 12 13 14 16 17 18 20 22 23 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 49 51 53 54 55 56 decoupling digital supply black peak hold capacitor I2C-bus serial clock input I2C-bus serial data input/output band gap decoupling chrominance input (S-VHS) external CVBS/Y input main supply voltage (+8 V) internal CVBS input ground 1 picture-in-picture output decoupling filter tuning external CVBS input RGB insertion input 2 red input 2 green input 2 blue input 2 black-current input blue output green output red output beam current limiter input red input 1 green input 1 blue input 1 RGB insertion input 1 luminance input luminance output -(B-Y) signal output -(R-Y) signal output -(B-Y) signal input -(R-Y) signal input 3.58 MHz crystal connection TDA8376; TDA8376A DESCRIPTION 4.43/3.58 MHz crystal connection loop filter phase detector SECAM reference output horizontal oscillator supply voltage (+8 V) CVBS/TXT output 1996 Jan 26 6 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A PIN SYMBOL SDIP52 SCO HOUT FBI GND2 PH2LF PH1LF GND3 EWD VDR(p) VDR(n) EHTO VSC Iref n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. VP3 GND4 GND5 39 40 41 42 43 44 45 46 47 48 49 50 51 52 - - - - - - - - - - - - QFP64 57 58 59 24 62 63 60 1 3 4 5 7 8 2 6 9 10 15 19 33 48 50 52 21 61 64 sandcastle output horizontal output flyback input ground 2 phase-2 filter phase-1 filter ground 3 east-west drive output vertical drive 1 positive output vertical drive 2 negative output EHT/overvoltage protection input vertical sawtooth capacitor reference current input not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected supply voltage 3 (+8 V) ground 4 ground 5 DESCRIPTION 1996 Jan 26 7 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A handbook, halfpage DECDIG CBLK SCL SDA DECBG CHROMA CVBS/Y VP1 CVBSINT 1 2 3 4 5 6 7 8 9 52 n.c. 51 Iref 50 VSC 49 EHTO 48 VDR(n) 47 VDR(p) 46 EWD 45 GND3 44 PH1LF 43 PH2LF 42 GND2 41 FBI 40 HOUT GND1 10 PIPO 11 DECFT 12 CVBSEXT 13 RGBIN2 14 RI2 15 GI2 16 BI2 17 BLKIN 18 BO 19 GO 20 RO 21 BCLIN 22 RI1 23 GI1 24 BI1 25 RGBIN1 26 MGE076 TDA8376(A) 39 SCO 38 CVBS/TXT 37 VP2 36 SECref 35 DET 34 XTAL2 33 XTAL1 32 RYI 31 BYI 30 RYO 29 BYO 28 LUMOUT 27 LUMIN Fig.2 Pin configuration (SDIP52). 1996 Jan 26 8 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A handbook, full pagewidth 56 CVBS/TXT 54 SECref 63 PH1LF 62 PH2LF 58 HOUT 61 GND4 64 GND5 60 GND3 57 SCO 53 DET 55 VP2 52 n.c. 51 50 49 48 47 46 45 44 43 EWD n.c. VDR(p) VDR(n) EHTO n.c. VSC Iref n.c. n.c. DECDIG CBLK SCL SDA n.c. DECBG CHROMA CVBS/Y n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VP1 20 VP3 21 CVBSINT 22 GND1 23 GND2 24 PIPO 25 DECFT 26 CVBSEXT 27 RGBIN2 28 RI2 29 GI2 30 BI2 31 BLKIN 32 59 FBI XTAL2 n.c. XTAL1 n.c. RYI BYI RYO BYO LUMOUT LUMIN RGBIN1 BI1 GI1 RI1 BCLIN RO GO BO n.c. MGE077 TDA8376(A) 42 41 40 39 38 37 36 35 34 33 Fig.3 Pin configuration (QFP64). 1996 Jan 26 9 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 7 7.1 FUNCTIONAL DESCRIPTION Video switches TDA8376; TDA8376A The circuit has two CVBS inputs and a Super-Video Home System (S-VHS) input. The input can be chosen by the I2C-bus. The input selector also has a position in which CVBSEXT is processed, unless there is a signal on the S-VHS input. When the input selector is in this position it switches to the S-VHS input if the S-VHS detector detects sync pulses on the S-VHS luminance input. The S-VHS detector output can be read by the I2C-bus. When the S-VHS option is not used the luminance input can be used as a second input for external CVBS signals. The choice is made via the CVS bit (see Table 1). The video switch circuit has two outputs which can be programmed in a different way. The input signal for the decoder is also available on the TXT output. Therefore this signal can be used to drive the teletext decoder and the SECAM add-on decoder. The signal on the PIP output can be chosen independent of the TXT output. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. The circuit contains a video identification circuit which checks whether a video signal is available at the selected video input. This circuit is independent of the synchronization circuit. The information of this identification circuit can also be used to switch the phase-1 (1) loop to a low gain when no signal is received so that a stable OSD display is obtained. The video identification circuit can be switched on and off via the I2C-bus. 7.2 Integrated video filters, peaking and black stretcher This provides a better picture impression than a symmetrical peaking. The circuit contains a coring circuit to prevent the noise content of the video signal being amplified by the peaking circuit. This coring circuit can be switched-off when required. It is possible to connect a Colour Transient Improvement (CTI) or Picture Signal Improvement (PSI) IC to the TDA8376. The luminance signal which has passed the filter and delay line circuit is available externally. The output signal of the transient improvement circuit must be applied to the luminance input circuit. When the CTI function is not required the two pins must be AC-coupled. The luminance signal below 50 IRE can be stretched in accordance with the difference between the peak black level and the blanking level of the back-porch of the video signal. The black level stretcher can be switched-off by connecting pin 2 to the positive supply line. 7.3 Synchronization circuit The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is only used to detect whether the line oscillator is synchronized and not for transmitter identification. The first Phase-Locked Loop (PLL) has a very high-statical steepness so that the phase of the picture is independent of the line frequency. To prevent the horizontal synchronization being disturbed by anti-copy signals such as Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The position of this pulse is asymmetrical and the width is approximately 22 s. The horizontal output signal is generated by an oscillator which operates at twice the line frequency. Its frequency is divided-by-two to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched on. The circuit contains a chrominance bandpass and trap circuit. The chrominance trap filter in the luminance path is designed for a symmetrical step response behaviour. The filters are realized by gyrator circuits and they are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by gyrator circuits. During SECAM reception the centre frequency of the chrominance trap is set to a value of approximately 4.2 MHz to obtain a better suppression of the SECAM carrier frequencies. The peaking function is achieved by two luminance delay cells each with a delay of 165 ns. The resulting peaking frequency is 3 MHz. The peaking is asymmetrical so that the overshoots in the direction of `black' are approximately two times higher than those in the direction of `white'. 1996 Jan 26 10 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors To obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty factor of the output pulse has such a value that maximum safety is obtained for the output stage To protect the horizontal output transistor the horizontal drive is switched off when a power-on reset is detected. The drive signal is switched on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. To prevent the horizontal output transistor being switched on during flyback the horizontal drive output is gated with the flyback pulse. The vertical sawtooth generator drives the vertical output and E-W correction drive circuits. The geometry processing circuits provide control of horizontal shift, E-W width, E-W parabola/width ratio, E-W corner/parabola ratio, trapezium correction, vertical shift, vertical slope, vertical amplitude, and the S-correction. All these controls can be set via the I2C-bus. The geometry processor has a differential current output for the vertical drive signal and a single-ended output for the E-W drive. Both the vertical drive and the E-W drive outputs can be modulated for EHT compensation. The EHT compensation pin is also used for overvoltage protection. The TDA8376A geometry processor also offers the possibility for a flexible vertical and horizontal zoom mode for 16 : 9 applications. Because of this feature an additional control can be added on the remote control so that the viewer can adjust the picture. In addition the de-interlace of the vertical output can be set via the I2C-bus. To avoid damage of the picture tube when the vertical deflection fails, the guard output current of the TDA8350 can be supplied to the sandcastle output. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I2C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled by the EVG bit of subaddress 0A (see Table 1). 7.4 TDA8376; TDA8376A Colour decoder The colour decoder contains an alignment-free crystal oscillator, a killer circuit and the colour difference demodulators. The 90 phase shift for the reference signal is made internally. The demodulation angle and gain ratio for the colour difference signals for PAL and NTSC are adapted to the standard. The colour decoder is very flexible. Together with the SECAM decoder TDA8395 an automatic multistandard decoder can be designed. In the automatic mode the SECAM identification is accepted only when the vertical frequency is 50 Hz. In the forced mode the system can also identify signals with a vertical frequency of 60 Hz. Which standard the IC can decode depends on the external crystals. If a 4.4 MHz and a 3.5 MHz crystal are used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be decoded. If two 3.5 MHz crystals are used PAL N and M can be decoded. If one crystal is connected only PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The crystal frequency of the decoder is used to tune the line oscillator. Therefore the value of the crystal frequency must be given to the IC via the I2C-bus. For a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (XA and XB) are not corrupted (see Table 6). For this reason the crystal bits (SXA and SXB) can be read in the output bytes so that the software can check the I2C-bus transmissions (see Table 38). 7.5 RGB output circuit and black-current stabilization The colour-difference signals are matrixed with the luminance signal to obtain the RGB-signals. For the RGB-inputs linear amplifiers have been chosen so that the circuit is suited for signals coming from the SCART connector. The RGB2 inputs (pins 14 to 17) have priority over the RGB1 inputs (pins 23 to 26). Both fast blanking inputs can be blocked by I2C-bus controls. The contrast and brightness controls operate on internal and external signals. 1996 Jan 26 11 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors The output signal has an amplitude of approximately 2 V black-to-white at nominal input signals and nominal settings of the controls. The black current stabilization is realized by feedback from the video output amplifiers to the RGB control circuit. The `black current' of the 3 guns of the picture tube is internally measured and stabilized. The black level control is active during 4 lines at the end of the vertical blanking. During the first line the leakage current is measured and the following 3 lines the 3 guns are adjusted to the required level. The maximum acceptable leakage current is 100 A. The nominal value of the `black current' is 10 A. The ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point. The input impedance of the `black-current' measuring pin is 15 k. Therefore the beam current during scan will cause the input voltage to exceed the supply voltage. The internal protection will start conducting so that the excessive current is bypassed. When the TV receiver is switched on the black current stabilization circuit is not active, the RGB outputs are blanked and beam current limiting input pin is short-circuited. Only during the measuring lines will the outputs supply a voltage of 5 V to the video output stage so that it can be detected if the picture tube is warming up. These pulses are switched on after a waiting time of approximately 0.5 s. This ensures that the vertical deflection is activated so that the measuring pulses are not visible on the screen. As soon as the current supplied to the measuring input exceeds a value of 190 A the stabilization circuit is activated. After a waiting time of approximately 0.8 s the blanking and the beam current limiting input pin are released. The remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. 8 TDA8376; TDA8376A I2C-BUS SPECIFICATION handbook, halfpage A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0 1 R/W 1/0 MLA743 Fig.4 Slave address (8A). Valid subaddresses: 00 to 13 (TDA8376) or 00 to 16 (TDA8376A); subaddress FE is reserved for test purposes. Auto-increment mode is available for subaddresses. 8.1 Start-up procedure Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, the procedure previously mentioned must be carried out to restart the IC. When this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip. 1996 Jan 26 12 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 8.2 Inputs Input status bits FUNCTION Source select Decoder mode Hue Horizontal shift (HS) E-W width (E-W) E-W parabola/width (PW) E-W corner parabola (CP) E-W trapezium (TC) Vertical slope (VS) Vertical amplitude (VA) S-correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast Spare Spare Spare Vertical zoom (VX, 76A) Note SUBADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 TDA8376; TDA8376A Table 1 DATA BYTE D7 INA 0 0 0 0 0 0 NCIN VID HCO SBL EXP(1) 0 MAT YD3 RBL IE1 0 0 0 0 0 D6 INB 0 0 0 0 0 0 0 LBM EVG PRD CL(1) CVS 0 YD2 COR IE2 0 0 0 0 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 YD1 A5 A5 A5 0 0 0 A5 D4 IND STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 YD0 A4 A4 A4 0 0 0 A4 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 0 0 A3 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 0 0 A2 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 0 0 A1 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 0 0 A0 FORF FORS 1. The bits EXP and CL in subaddress 0C are only valid for the TDA8376. For the TDA8376A these two bits must be set to logic 0. Table 2 Output status bits FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 Note 1. X = don't care. DATA BYTE D7 POR NDF D6 FSI IN1 D5 STS IN2 D4 SL IFI D3 XPR AFA D2 CD2 X(1) D1 CD1 SXA D0 CD0 SXB 1996 Jan 26 13 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 8.2.1 Table 3 INA 0 0 1 1 Table 4 INC 0 0 1 1 Table 5 FOA 0 0 1 Note 1. X = don't care. Table 6 XA 0 0 1 1 Crystal indication XA and XB XB 0 1 0 1 two 3.6 MHz one 3.6 MHz (pin 33) one 4.4 MHz (pin 34) 3.6 MHz (pin 33) and 4.4 MHz (pin 34) CRYSTAL INPUT CONTROL BITS Source select 1 INB 0 1 0 1 DECODER AND TXT CVBSINT CVBSEXT S-VHS S-VHS (CVBSEXT) Table 7 FORF 0 0 1 1 Note PIP CVBSINT CVBSEXT S-VHS S-VHS (CVBSEXT) Table 8 DL 0 1 Table 9 STB 0 1 standby normal interlace Interlace TDA8376; TDA8376A Forced field frequency FORS 0 1 0 1 FIELD FREQUENCY auto (60 Hz when line not synchronized) 60 Hz; note 1 50 Hz; note 1 auto (50 Hz when line not synchronized) Source select 2 IND 0 1 0 1 1. When the forced mode is selected the divider will only switch to that position when the horizontal oscillator is not synchronized. STATUS de-interlace Standby MODE Phase 1 (1) time constant FOB 0 1 X(1) normal slow fast MODE Table 10 Synchronization mode POC 0 1 active not active MODE Table 11 Colour decoder mode CM2 0 0 0 0 1 1 1 1 CM1 0 0 1 1 0 0 1 1 CM0 0 1 0 1 0 1 0 1 DECODER MODE not forced, own intelligence forced NTSC 3.6 MHz forced PAL 4.4 MHz forced SECAM forced NTSC 4.4 MHz forced PAL 3.6 MHz (pin 33) forced PAL 3.6 MHz (pin 34) no function 1996 Jan 26 14 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors Table 12 Vertical divider mode NCIN 0 1 VERTICAL DIVIDER MODE normal operation switched to search window TDA8376; TDA8376A Table 20 Condition Y/C input CVS 0 1 Y-INPUT MODE switched to Y/C mode switched to CVBS mode Table 13 Video identification mode VID 0 1 VIDEO IDENTIFICATION MODE 1 loop switched on and off not active Table 21 PAL/NTSC matrix MAT 0 1 PAL MATRIX adapted to standard Table 14 Long blanking mode LBM 0 1 BLANKING MODE adapted to standard (50 or 60 Hz) fixed in accordance with 50 Hz standard Table 22 Y-delay adjustment; note 1 YD0 to YD3 YD3 YD2 YD1 YD0 Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. This is only valid for a CVBS signal without group delay distortions. Table 23 RGB blanking RBL 0 not active active 1 RGB BLANKING YD2 x 80 ns + YD1 x 40 ns + YD0 x 40 ns Y-DELAY YD3 x 160 ns + Table 15 EHT tracking mode HCO 0 1 TRACKING MODE EHT tracking only on vertical EHT tracking on vertical and E-W Table 16 Enable vertical guard (RGB blanking) EVG 0 1 active VERTICAL GUARD MODE not active Table 17 Service blanking SBL 0 1 off on SERVICE BLANKING MODE Table 24 Noise coring (peaking) COR 0 off on 1 NOISE CORING Table 18 Overvoltage input mode PRD 0 1 OVERVOLTAGE MODE detection mode protection mode Table 25 Enable fast blanking RGB1 IE1 0 not active active 1 FAST BLANKING Table 19 Vertical deflection mode (TDA8376 only) EXP 0 0 1 1 1996 Jan 26 CL 0 1 0 1 VERTICAL DEFLECTION MODE normal compress expand expand and lift 15 Table 26 Enable fast blanking RGB2 IE2 0 1 not active active FAST BLANKING Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 8.2.2 OUTPUT CONTROL BITS TDA8376; TDA8376A Table 33 Output vertical guard NDF VERTICAL OUTPUT STAGE OK failure Table 27 Power-on reset POR 0 1 normal power-down MODE 0 1 Table 34 Indication RGB1 insertion IN1 0 1 RGB INSERTION no (pin 26 LOW) yes (pin 26 HIGH) Table 28 Field frequency indication FSI 0 1 50 Hz 60 Hz FREQUENCY Table 35 Indication RGB2 insertion IN2 S-VHS INPUT 0 1 RGB INSERTION no (pin 14 LOW) yes (pin 14 HIGH) Table 29 S-VHS status STS 0 1 no signal signal Table 36 Output video identification IFI 0 1 VIDEO SIGNAL no video signal identified video signal identified Table 30 Phase 1 (1) lock indication SL 0 1 not locked locked INDICATION Table 37 IC version indication AFA 0 1 TDA8376 TDA8376A IC Table 31 X-ray protection XPR 0 1 OVERVOLTAGE no overvoltage detected overvoltage detected Table 38 Crystal indication SXA and SXB SXA STANDARD 0 0 1 1 SXB 0 1 0 1 two 3.6 MHz one 3.6 MHz one 4.4 MHz 3.6 and 4.4 MHz CRYSTAL Table 32 Colour decoder mode CD2 0 0 0 0 1 1 1 1 CD1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 no colour standard identified NTSC 3.6 MHz PAL 4.4 MHz SECAM NTSC 4.4 MHz PAL 3.6 MHz (pin 33) PAL 3.6 MHz (pin 34) spare 1996 Jan 26 16 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Tstg Tamb Tsol Tj Ves PARAMETER supply voltage storage temperature operating ambient temperature soldering temperature operating junction temperature electrostatic handling all pins; notes 1 and 2 all pins; notes 1 and 3 Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 k; C = 100 pF. 3. Machine Model (MM): R = 0 ; C = 200 pF. 10 THERMAL CHARACTERISTICS SYMBOL Rth j-a SDIP52 QFP64 11 QUALITY SPECIFICATION PARAMETER thermal resistance from junction to ambient in free air for 5 s CONDITIONS TDA8376; TDA8376A MIN. - -25 0 - - -2000 -200 MAX. 9.0 +150 70 260 150 +2000 +200 V UNIT C C C C V V VALUE 40 50 UNIT K/W K/W In accordance with "SNW-FQ-611E". The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9398 510 63011. 11.1 Latch-up At Tamb = 70 C all pins meet the following specification. * Itrigger 100 mA or 1.5VDD(max) * Itrigger -100 mA or -0.5VDD(max). 1996 Jan 26 17 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 12 CHARACTERISTICS VP = 8 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies MAIN SUPPLY (PIN 8) VP1 IP1 Ptot VP2 IP2 supply voltage supply current total power dissipation PARAMETER CONDITIONS TDA8376; TDA8376A MIN. TYP. MAX. UNIT 7.2 - - 7.2 - 8.0 75 650 8.8 - - 8.8 - V mA W HORIZONTAL OSCILLATOR SUPPLY (PIN 37) supply voltage supply current 8.0 6 V mA CVBS and S-VHS input switch INTERNAL AND EXTERNAL CVBS INPUTS (PINS 9 AND 13) V9(p-p) I9 SSCVBS CVBS input voltage (peak-to-peak value) CVBS input current suppression of non-selected CVBS input signal notes 2 and 3 note 1 - - 50 1.0 4 - 1.4 - - V A dB S-VHS INPUT (PINS 6 AND 7) V7(p-p) I7(p-p) V6(p-p) luminance input voltage (peak-to-peak value) luminance input current chrominance input voltage (burst amplitude) (peak-to-peak value) chrominance input impedance note 4 - - - 1.0 4 0.3 1.4 - 0.45 V A V Zi Vo(p-p) Zo VTS - - - - 50 - - 250 - k TXT AND PIP OUTPUT SIGNALS (PINS 38 AND 11) output signal voltage amplitude (peak-to-peak value) output impedance top sync voltage level 1.0 - tbf V V 1996 Jan 26 18 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RGB inputs, colour difference inputs, luminance inputs and outputs RGB INPUTS (PINS 15 TO 17 AND 23 TO 25); note 5 Vi(p-p) input signal voltage amplitude for an output signal of 2 V (black-to-white) at nominal controls (peak-to-peak value) input signal voltage amplitude before clipping occurs (peak-to-peak value) difference between black level of internal and external signals at the outputs input currents delay difference for the three channels no clamping; note 7 note 2 note 6 - 0.7 0.8 V Vi(p-p) note 2 1.0 - - V Vo - - 20 mV Ii td - - 0.1 0 - 20 A ns FAST BLANKING (PINS 14 AND 26) Vi V14,26(max) td td input voltage maximum input pulse delay time from RGB input to RGB output delay difference between data insertion to RGB output and RGB input to RGB output input current suppression of internal RGB signals notes 1 and 2; data insertion; fi = 0 to 5 MHz suppression of external RGB signals notes 1 and 2; no data insertion; fi = 0 to 5 MHz input voltage to insert black level at the RGB outputs to facilitate OSD signals being applied to the outputs input signal amplitude -(R-Y) (peak-to-peak value) input signal amplitude -(B-Y) (peak-to-peak value) input current for both inputs no data insertion data insertion data insertion data insertion; note 5 data insertion; note 5 - 0.9 - - - - - - 100 50 0.4 - 3.0 - - V V V ns ns I14,26 SSint SSext V14 - 55 55 4 - - - - 0.2 - - - mA dB dB V COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32) V32(p-p) V31(p-p) I31,32 note 7 note 7 note 7 - - - 1.05 1.35 0.1 - - 1.0 V V A 1996 Jan 26 19 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS - - - - - no clamping - MIN. TYP. MAX. UNIT LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28) V28(p-p) VTS Zo V27(p-p) Iclamp Ii output signal voltage amplitude (peak-to-peak value) top sync voltage level output impedance input signal voltage amplitude (peak-to-peak value) clamping current during burst key pulse input current top sync to white 0.45 2.5 250 0.45 200 - 0.63 - - - - 0.5 V V V A A Chrominance filters CHROMINANCE TRAP CIRCUIT ftrap QF SR trap frequency during SECAM reception trap quality factor colour subcarrier rejection note 8 - - - 20 - - fosc 4.2 2 - fosc 3 - - - - - - dB MHz MHz CHROMINANCE BAND-PASS CIRCUIT fc QBP centre frequency band-pass quality factor MHz Delay line, peaking circuit and black stretcher Y DELAY LINE td td1 B delay time tuning range delay time bandwidth of internal delay line note 2 8 steps note 2 - -160 5 - at 50% of pulse; note 2 positive negative peaking control curve GW CORING STAGE S coring range - 15 100% of peak-white 50% of peak-white 15% of peak-white -1 -1 6 15 - 27 +1 +3 10 IRE wave gain 16 steps negative half wave gain ------------------------------------------------------------positive half wave gain - - - - 480 - - 3 160 20 36 see Fig.5 1.8 - - +160 - - - - - ns ns MHz PEAKING CONTROL; note 9 fc(p) tW OS peaking centre frequency width of preshoot or overshoot overshoot MHz ns % % BLACK LEVEL STRETCHER (PIN 2); note 10 BLSmax LSH maximum black level shift level shift 21 0 - 8 IRE IRE IRE IRE 1996 Jan 26 20 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Horizontal synchronization circuits SYNC VIDEO INPUTS (PINS 7, 9 AND 13) V7,9,13 SLHS SLVS ffr ffr f/VP f(max) sync pulse voltage amplitude slicing level for horizontal sync slicing level for vertical sync note 7 note 11 50 - - - - VP = 8 V 10%; note 2 Tamb = 0 to 70 C; note 2 - - 300 50 30 - - - - 2 0.5 80 mV % % HORIZONTAL OSCILLATOR free running frequency spread of free running frequency frequency variation with respect to the supply voltage maximum frequency variation with temperature 15625 - 0.2 - Hz % % Hz FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 44); note 12 fHR fCR S/N frequency holding range PLL frequency catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 2 - 0.6 - 0.9 0.9 20 1.2 - - kHz kHz dB HYS i/o tcr - - 11 1 - - - dB s/s s SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 43) control sensitivity control range from start of horizontal output to flyback at nominal shift position horizontal shift range control sensitivity for dynamic compensation voltage to switch on the `flash' protection input current during protection note 13 63 steps 150 12 tshift dync V43 I43 VOL IO(max) VO(max) 2 - 6 - - 5.3 - - - - - 50 75 2fHOUT 50 100 50 - - - 1 s s/V V mA HORIZONTAL OUTPUT (PIN 40); note 14 LOW level output voltage maximum allowed output current maximum allowed output voltage duty factor note 2 note 2; VHOUT = high; during switch-on/switch-off fswitch tswitch(on) tswitch(off) frequency during switch-on and switch-off switch-on time switch-off time RGB drive maximum RGB drive minimum 1996 Jan 26 21 IOL = 10 mA - 10 - - - - - - - 0.3 - VP - - - - - - V mA V % % Hz ms ms ms Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS - - note 7 note 7 - - MIN. TYP. MAX. - - - - 5.8 2.2 3.7 - - - 0.5 - - UNIT FLYBACK PULSE INPUT (PIN 41) VHSW V2(SW) V41(max) Zi V39 tW switching voltage level for horizontal blanking switching level for phase-2 loop maximum input voltage input impedance 0.4 4.0 8.0 10 V V V M SANDCASTLE PULSE OUTPUT (PIN 39) output voltage pulse width during burst key during blanking burst key pulse vertical blanking (50 Hz) vertical blanking (60 Hz) Vclamp I39(min) I39(max) td clamping voltage level for vertical guard detection minimum input current to activate guard detection maximum allowable input current delay of start of burst key to start of sync 4.8 1.8 3.3 - - - - 2.5 - 5.3 2.0 3.5 25 21 2.7 - - 5.4 V V s lines lines V mA mA s Vertical synchronization and geometry correction VERTICAL OSCILLATOR; note 15 ffr flock LR free running frequency locking frequency range divider value not locked locking range - 45 - 488 50/60 - 625/525 - - 64.5 - 722 Hz Hz lines lines/ frame VERTICAL RAMP GENERATOR (PIN 50) V50(p-p) Idis Icharge VS I50 V50L Idiff(p-p) ICM Vo sawtooth voltage amplitude (peak-to-peak value) discharge current charge current set by external resistor vertical slope control range charge current increase LOW level voltage of ramp note 16 63 steps f = 60 Hz VS = 1FH; C = 100 nF; R = 39 k - - - -20 - - VA = 1FH - - 0 3.5 1 19 - 20 2.07 - - - +20 - - - - 4.0 V mA A % % V VERTICAL DRIVE OUTPUTS (PINS 47 AND 48) differential output current (peak-to-peak value) common mode output current output voltage 0.95 400 - mA A V 1996 Jan 26 22 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS MIN. - - TYP. MAX. UNIT EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 49); note 13 V49 SMR vert EW Ieq V49 DE-INTERLACE first field delay E-W WIDTH; note 17 CR control range TDA8376 TDA8376A Ieq equivalent output current TDA8376 TDA8376A Vo Io E-W output voltage range E-W output current range TDA8376 TDA8376A E-W PARABOLA/WIDTH CR Ieq CR Ieq CR Ieq CR Ieqdiff(p-p) control range equivalent output current 63 steps E-W = 3FH; CP = 00H 0 0 -43 -190 -5 -100 63 steps SC = 00H 80 760 - - - - - - - - 22 440 % A % A % A % A 0 0 - - 900 1200 A A 0 0 1.0 - - - 400 700 8.0 A A V 63 steps 100 100 - - 80 65 % % - 0.5H - input voltage scan modulation range vertical sensitivity E-W sensitivity E-W equivalent output current overvoltage detection level when switched-on 1.2 -5 - - +100 - 2.8 +5 - - -100 - V % %/V %/V A V 6.3 -6.3 - 3.9 E-W CORNER/PARABOLA control range equivalent output current 63 steps PW = 3FH; E-W = 3FH 0 0 E-W TRAPEZIUM control range equivalent output current 63 steps +5 +100 VERTICAL AMPLITUDE control range equivalent differential vertical drive output current (peak-to-peak value) 120 1140 VERTICAL SHIFT CR Ieqdiff(p-p) control range equivalent differential vertical drive output current (peak-to-peak value) 63 steps -5 -50 - - +5 +50 % A S-CORRECTION CR 1996 Jan 26 control range 63 steps 23 0 - 30 % Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VERTICAL EXPANSION (ZOOM) MODE (TDA8376A ONLY); note 18 Output current variation compared with nominal scan: VEF vertical expansion factor output current limiting and RGB blanking Colour demodulation part CHROMINANCE AMPLIFIER ACCcr V THRon HYSoff ACC control range variation in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong signal conditions; S/N 40 dB; note 2 noisy input signals; note 2 REFERENCE PART note 19 26 - -23 - - - - -26 +3 +1 - 2 -29 - - dB dB dB dB dB 0.75 - - 1.06 1.38 - % % Phase-locked loop; note 20 fCR frequency catching range phase shift for a 400 Hz deviation of the oscillator frequency note 2 360 - 600 - - 2 Hz deg Oscillator TCosc fosc Ri(min) CL(max) HUE CONTROL HUEcr HUE HUE/T hue control range hue variation for 10% VP hue variation with temperature 63 steps; see Fig.6 note 2 Tamb = 0 to 70 C; note 2 35 - - 40 0 0 - - - deg deg deg temperature coefficient of the oscillator frequency oscillator frequency deviation with respect to the supply minimum negative input resistance maximum load capacitance note 2 note 2; VP = 8 V 10% - - - - - - - - tbf tbf 1 15 Hz/K Hz k pF 1996 Jan 26 24 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER -(R-Y) output voltage amplitude (peak-to-peak value) -(B-Y) output voltage amplitude (peak-to-peak value) gain ratio between both demodulators G(B-Y) and G(R-Y) spread of voltage amplitude ratio PAL/NTSC output impedance -(R-Y)/-(B-Y) output bandwidth of demodulators residual carrier output (peak-to-peak value) note 2 note 2 CONDITIONS - - MIN. TYP. MAX. - - 1.96 +1 - - 5 5 5 5 25 - 0.1 5 UNIT DEMODULATORS (PINS 29 AND 30) V30(p-p) V29(p-p) G V Zo B V29,30(p-p) note 21 note 21 0.525 0.675 1.78 - 500 650 - - - - - 0.1 - - V V 1.60 -1 - - - - - - - - - - dB kHz mV mV mV mV mV %/K dB deg -3 dB; notes 7 and 21 f = fosc; -(R-Y) output f = fosc; -(B-Y) output f = 2fosc; -(R-Y) output f = 2fosc; -(B-Y) output V30(p-p) Vo/T Vo/VP e H/2 ripple at -(R-Y) output (peak-to-peak value) variation of output voltage amplitude note 2 with temperature variation of output voltage amplitude note 2 with supply voltage phase error in the demodulated signals COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT PAL or (SECAM mode with TDA8395); -(R-Y) and -(B-Y) not affected (G-Y)/(R-Y) ratio of demodulated signals (G-Y)/(B-Y) ratio of demodulated signals - - -0.51 10% -0.19 25% -(B-Y) 1.39(R-Y) - 0.07(B-Y) -0.46(R-Y) - 0.15(B-Y) - - NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting) -(B-Y) -(R-Y) -(G-Y) -(B-Y) signal -(R-Y) signal -(G-Y) signal 1996 Jan 26 25 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS - MIN. TYP. MAX. - 0.3 - - UNIT REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 36); note 22 fref V36(p-p) Vo reference frequency output voltage amplitude (peak-to-peak value) output voltage level PAL/NTSC identified no PAL/NTSC identified; SECAM (by TDA8395) identified I36 Control part SATURATION CONTROL; note 6 SATCR CONCR saturation control range 63 steps; see Fig.7 52 - - - 20 - - - 0.5 dB required current to stop PAL/NTSC identification circuit during SECAM 4.43 0.25 1.5 5.0 MHz V V V 0.2 - - 150 - - A CONTRAST CONTROL; note 6 contrast control range 63 steps dB dB tracking between the three channels see Fig.8 over a control range of 10 dB BRIGHTNESS CONTROL BRICR V19,20,21(p-p) brightness control range 63 steps; see Fig.9 - tbf 0.7 2.0 - tbf V RGB OUTPUT SIGNALS (PINS 19, 20 AND 21) output voltage amplitude (peak-to-peak value) at nominal luminance input signal, nominal contrast and white-point adjustment; note 6 at maximum white point setting VBWmax(p-p) maximum voltage amplitude (black-to-white) note 23 at maximum white point setting V - - - tbf 3.0 2.6 3.6 2.1 - - - tbf V V V V VRED(p-p) output voltage amplitude for the `red' at nominal settings for channel (peak-to-peak value) contrast and saturation control and no luminance signal to the input (R-Y, PAL) blanking level at the RGB outputs internal bias current of NPN emitter follower output transistor available output current output impedance control range of the black-current stabilization Vblank Ibias Io Zo CRbl 0.7 - - - nominal brightness and - white-point adjustment (with respect to the measuring pulse); Vblk = 2.5 V 26 0.8 1.5 5 150 - 0.9 - - - 1 V mA mA V 1996 Jan 26 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL Vbl Vo bl/T bl PARAMETER black level shift with picture content output voltage of the 4-L pulse after switch-on variation of black level with temperature relative variation in black level between the three channels during variations of supply voltage (10%) saturation (50 dB) contrast (20 dB) brightness (0.5 V) temperature (range 40 C) note 2 note 2 note 2 CONDITIONS - - - MIN. - TYP. 4.2 1.0 MAX. 20 - - UNIT mV V mV/K nominal controls nominal contrast nominal saturation nominal controls RGB input; note 24 CVBS input; note 24 at fosc at 2fosc plus higher harmonics in RGB outputs RGB input; at -3 dB CVBS input; at -3 dB; fosc = 3.58 MHz CVBS input; at -3 dB; fosc = 4.43 MHz S-VHS input; at -3 dB - - - - - 60 50 - - 8 - - 5 - 40 40 - - - - - - - - - - - - - 2.8 3.5 - 20H 50 50 tbf tbf tbf tbf tbf - - 15 15 - - - - - 60 60 - - - mV mV mV mV mV dB dB mV mV MHz MHz MHz MHz S/N Vres(p-p) signal-to-noise ratio of the output signals residual voltage at the RGB outputs (peak-to-peak value) bandwidth of output signals B WHITE-POINT ADJUSTMENT I2C-bus setting for nominal gain Ginc(max) Gdec(max) Ibias Ileak Iscan(max) maximum increase of the gain maximum decrease of the gain HEX code HEX code 3FH HEX code 00H % % A A mA BLACK-CURRENT STABILIZATION (PIN 18); note 25 bias current for the picture tube cathode acceptable leakage current maximum current during scan nominal white point setting 10 100 0.3 1996 Jan 26 27 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A SYMBOL PARAMETER CONDITIONS - - - - - - - MIN. TYP. MAX. - - - - - - - UNIT BEAM CURRENT LIMITING (PIN 22); note 23 VCR VdiffCR VBR VdiffBR Vbias Ich(int) Idisch Notes 1. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. This parameter is measured at nominal settings of the various controls. 4. Indicated is a signal for a colour bar with 75% saturation (chrominance : burst ratio = 2.2 : 1). 5. The RGB1 inputs (pins 14 to 17) have priority over the RGB2 inputs (pins 23 to 25). 6. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum -10 dB. In the nominal brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses. 7. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 8. The -3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f -3 dB = f osc 1 - ------- 2Q 9. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 10. For video signals with a black level which deviates from the back-porch blanking level the signal is `stretched' to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.10). The black level is detected by the capacitor connected to pin 2. The black level stretcher can be made inoperative by connecting pin 2 to the positive supply line. The values given are valid only when the luminance input signal (pins 7, 9 and 13) has a value of 1 V (p-p). 11. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction internal bias voltage internal charge current discharge current due to `peak-white limiting' 3.5 2.0 2.5 1.0 4.5 25 200 V V V V V A A 1996 Jan 26 28 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A 12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when too much noise is present in the signal. In the `fast' mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatically or overruled by the I2C-bus. The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be defeated via the I2C-bus. To prevent that the horizontal synchronization being disturbed by anti-copy guard signals like Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 s, the phase position around the sync pulse is asymmetrical. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various conditions are shown in Table 39. 13. The ICs have two protection inputs. The protection on pin 43 is intended to be used as `flash' protection. When this protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow start procedure. The protection on pin 49 is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive can be switched-off (via the slow stop procedure). It is also possible to continue the horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the two modes of operation is made via the PRD bit. 14. During switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (VHOUT = high). After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double value and the RGB drive is set to maximum so that the EHT capacitor is discharged. After approximately 100 ms the RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off. 15. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation: a) Search mode `large window'. This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode `narrow window'. This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz). When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider requires some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 08. 1996 Jan 26 29 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 16. Conditions: frequency is 50 Hz; normal mode; VS = 1FH. TDA8376; TDA8376A 17. The E-W output current range of the TDA8376A is higher than that of the TDA8376 because of the horizontal zoom function of the TDA8376A. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 A variation in E-W output current is equivalent to 20% variation in picture width. 18. The TDA8376A has a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 75 to 138% of the nominal scan. At an amplitude of 106% of the nominal scan the output current is limited and the blanking of he RGB outputs is activated. This is illustrated in Fig.21. In addition to the variation of the vertical amplitude the vertical slope control range is also increased. This allows variation of the position of the bottom part of the picture independent of the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical `zoom' DAC. 19. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)] the dynamic range of the ACC is +6 and -20 dB. 20. All frequency variations are referenced to a 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitance of 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the crystal. Provided the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal parameters for the crystals are: a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal) c) parallel capacitance C0 = 5 pF for both crystals. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures given in are therefore valid for the specified crystal series. In this, tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: CM Detuning range: ------------------------ C0 2 1 + ------ CL The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. For 3-normal applications with two crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pF. 21. The -(R-Y) and -(B-Y) signals are demodulated with a phase difference of the reference carrier of 90 and a gain - ( B - Y) ratio ----------------------- = 1.78 . The matrixing to the required signals is achieved in the control part. - ( R - Y) 22. The subcarrier output signal can be supplied to the TDA8395 but it can also be used as drive signal for external comb filters. For this reason the signal is continuously available at the output. Only when SECAM has been identified the subcarrier signal is available only during the vertical retrace time. This is to avoid cross-talk between the SECAM input signal and the subcarrier signal. An external DC load on this pin is not allowed because this current will disturb the reliability of the communication between the TDA8376/TDA8376A and the TDA8395. 23. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input. 24. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 25. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a result the `black-current' of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment. 1996 Jan 26 30 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors Table 39 Output current of the phase detector in the various conditions I2C-BUS COMMANDS VID - - - - - 0 - Note POC 0 0 0 0 0 0 1 FOA 0 0 0 0 1 - - FOB 0 0 1 1 - - - IC CONDITIONS IDENT yes yes yes yes yes no - COIN yes no yes yes - - - NOISE yes no yes no - - - TDA8376; TDA8376A -1 CURRENT/MODE SCAN 30 180 30 180 180 6 - V-RETR 30 270 30 270 270 6 - GATING yes(1) no yes yes no no - MODE auto auto slow fast fast OSD off 1. Only during vertical retrace, pulse width 22 s. In other conditions the pulse width is 5.7 s and the gating is continuous. MLA738 - 1 MLA739 - 1 50 (%) 30 (deg) 50 30 10 10 10 10 30 30 50 0 4 8 C F 10 DAC (HEX) 50 0 10 20 30 40 DAC (HEX) Overshoot in direction `black'. Fig.5 Peaking control curve. Fig.6 Hue control curve. 1996 Jan 26 31 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A MLA741 - 1 MLA740 - 1 250 (%) 225 200 175 150 125 100 75 50 25 0 0 10 20 30 40 DAC (HEX) 100 (%) 90 80 70 60 50 40 30 20 10 0 10 20 30 40 DAC (HEX) Fig.7 Saturation control curve. Fig.8 Contrast control curve. MLA742 - 1 MGE079 0.7 (V) 0.35 handbook, halfpage 100 80 output (IRE) 60 0 40 20 0.35 0 0.7 0 0 10 20 30 40 DAC (HEX) -20 0 A (1) A B B (2) 20 40 60 80 input (IRE) 100 Relative variation with respect to the measuring pulse. (1) Maximum black level shift. (2) Level shift at 15% of peak white. Fig.9 Brightness control curve. Fig.10 I/O relationship of the black level stretcher. 1996 Jan 26 32 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 13 TEST AND APPLICATION INFORMATION TDA8376; TDA8376A handbook, full pagewidth SDA SCL RI2 GI2 BI2 RGBIN2 RI1 GI1 BI1 RGBIN1 4 CVBSINT 9 3 15 16 17 14 23 24 25 26 21 20 RO GO BO BLKIN BCLIN EWD VDR(p) VDR(n) HOUT FBI CVBSEXT 13 19 18 CVBS/Y 7 TDA8376(A) 22 46 CHROMA 6 47 48 PIPO 11 34 XTAL2 4.4 MHz 33 XTAL1 3.6 MHz 38 CVBS/ TXT 36 SECref RYO 30 29 BYO 32 RYI 31 BYI 39 SCO 40 41 to text decoder TDA8395 TDA4665 MGE080 Fig.11 Application diagram. 13.1 East-West output stage In order to obtain correct tracking of the vertical and horizontal EHT-correction, the E-W output stage should be dimensioned as illustrated in Fig.12. Resistor REW determines the gain of the E-W output stage. Resistor Rc determines the reference current for both the vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 k which results in a reference current of 100 A (Vref = 3.9 V The value of REW must be: V scan R EW = R c x ---------------------18 x V ref Example: With Vref = 3.9 V Rc = 39 k and Vscan = 120 V then REW = 68 k. 1996 Jan 26 33 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A handbook, full pagewidth VDD HORIZONTAL DEFLECTION STAGE Vscan REW TDA8376(A) 46 EWD EW OUTPUT STAGE MGE081 DIODE MODULATOR VEW 51 Vref Rc 39 k (2%) Iref 50 Csaw 100 nF (5%) Fig.12 East-West output stage. handbook, halfpage 600 MGE082 MGE083 handbook, halfpage 900 700 500 300 Ivert (A) 400 Ivert (A) 200 0 100 -100 -300 -200 -400 -600 0 1/2 t time t -500 -700 0 1/2 t time t VA = 0, 31H and 63H; VSH = 31H; SC = 0. VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0. Fig.13 Control range of vertical amplitude. Fig.14 Control range of vertical slope. 1996 Jan 26 34 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A MGE084 MGE085 handbook, halfpage 600 handbook, halfpage 600 400 Ivert (A) 200 Ivert (A) 400 200 0 0 -200 -400 -600 0 1/2 t time t -200 -400 -600 0 1/2 t time t VSH = 0, 31H and 63H; VA = 31H; SC = 0. SC = 0, 31H and 63H; VA = 31H; VHS = 31H. Picture height does not change with setting of S-correction for nominal vertical amplitude (VA = 31H). Fig.15 Control range of vertical shift. Fig.16 Control range of S-correction. MGE086 MGE087 handbook, halfpage 1200 handbook, halfpage 900 1000 IEW (A) 800 IEW (A) 800 700 600 600 400 500 200 400 0 0 1/2 t time t 300 0 1/2 t time t EW = 0, 31H and 63H; PW = 31H; CP = 31H. PW = 0, 31H and 63H; EW = 31H; CP = 31H. Fig.17 Control range of E-W width. Fig.18 Control range of E-W parabola/width ratio. 1996 Jan 26 35 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A MGE088 handbook, halfpage 900 MGE089 handbook, halfpage 650 IEW (A) 800 IEW (A) 600 700 550 600 500 500 450 400 400 300 0 1/2 t time t 350 0 1/2 t time t CP = 0, 31H and 63H; EW = 31H; PW = 63H. TC = 0, 31H and 63H; EW = 31H; PW = 31H. Fig.19 Control range of E-W corner/parabola ratio. Fig.20 Control range of E-W trapezium correction. handbook, full pagewidth 70 60 vertical 50 position 40 (%) 30 20 10 0 -10 -20 -30 -40 -50 -60 TOP PICTURE 138% 100% 75% 1/2 t time t BOTTOM PICTURE blanking for expansion 138% MGE090 TDA8376A only. Fig.21 Sawtooth waveform and blanking pulse. 1996 Jan 26 36 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 13.2 Adjustment of geometry control parameters TDA8376; TDA8376A The deflection processor of the TDA8376/TDA8376A offers nine control parameters for picture alignment: * Vertical picture alignment - S-correction - vertical amplitude - vertical slope - vertical shift * Horizontal picture alignment - horizontal shift - E-W width - E-W parabola/width - E-W corner/parabola - E-W trapezium correction. It is important to notice that the TDA8376/ TDA8376A is designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). For a particular combination of picture tube type, vertical output stage and E-W output stage it is determined which are the required values for the settings of S-correction, E-W parabola/width ratio and E-W corner/parabola ratio. These parameters can be preset via the I2C-bus, and do not need any additional adjustment. The remainder of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV-set adjustments. The vertical shift control is intended for compensation of off-sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the value of the off-set, and to the square of the S-correction required. The necessity to use the vertical shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the S-correction, and on the demands upon vertical linearity. For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SB-bit HIGH. In this mode the RGB-outputs are blanked during the second half of the picture. There are two different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the correct setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1FH). Then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the E-W width and the horizontal shift. Finally (if necessary) the left and right-hand sides of the picture are aligned in parallel by adjusting the E-W trapezium control. To obtain the full range of the vertical zoom function of the TDA8376A the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19H. 1996 Jan 26 37 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 14 PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) TDA8376; TDA8376A SOT247-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 52 27 pin 1 index E 1 26 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 90-01-22 95-03-11 1996 Jan 26 38 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors TDA8376; TDA8376A QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 52 33 32 ZE A e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L pin 1 index wM e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 1996 Jan 26 39 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 15 SOLDERING 15.1 Introduction TDA8376; TDA8376A There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 15.2.1 SDIP SOLDERING BY DIPPING OR BY WAVE Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. 15.3.2 WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 REPAIRING SOLDERED JOINTS The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3 15.3.1 QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1996 Jan 26 40 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA8376; TDA8376A This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jan 26 41 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors NOTES TDA8376; TDA8376A 1996 Jan 26 42 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processors NOTES TDA8376; TDA8376A 1996 Jan 26 43 Philips Semiconductors - a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/01/pp44 Document order number: Date of release: 1996 Jan 26 9397 750 00592 |
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